DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 365
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.
5.
6.
7.
9.8
9.8.1
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Module stop mode cannot be set during DTC operation. For details, refer to section 24,
Power-Down Modes.
9.8.2
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR should not be cleared to 0.
9.8.3
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are masked, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is
H'E0.
Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
If the write was successful, the DTC is activated and a block of 128 bytes of data is
transferred.
After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should
clear the SWDTE bit to 0 and perform other wrap-up processing.
Usage Notes
Module Stop Mode Setting
On-Chip RAM
DTCE Bit Setting
Rev. 6.00 Mar. 18, 2010 Page 303 of 982
Section 9 Data Transfer Controller (DTC)
REJ09B0054-0600
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