DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 225
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.4
6.4.1
PBC operation can be disabled or enabled using the module stop control register. The initial
setting is for PBC operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 24, Power-Down Modes.
6.4.2
The PC break interrupt is shared by channels A and B. The channel from which the request was
issued must be determined by the interrupt handler.
6.4.3
The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or
CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt
will be requested after interrupt handling ends.
6.4.4
A PC break interrupt generated when the DTC and DMAC* is the bus master is accepted after the
bus has been transferred to the CPU by the bus controller.
Note: * Supported only by the H8S/2239 Group.
6.4.5
Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS
instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the
instruction fetch at the next address.
Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
PC Break Interrupts
PC Break Interrupt when DTC and DMAC* Is Bus Master
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA,
Usage Notes
Module Stop Mode Setting
CMFA and CMFB
RTE, and RTS Instruction
Rev. 6.00 Mar. 18, 2010 Page 163 of 982
Section 6 PC Break Controller (PBC)
REJ09B0054-0600
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