DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 656
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 594 of 982
REJ09B0054-0600
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Figure 15.12 Sample Serial Reception Data Flowchart (1)
PER ∨ FER ∨ ORER = 1
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
All data received?
FER flags in SSR
Start reception
Initialization
RDRF = 1
<End>
Yes
Yes
No
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] [3] Receive error processing and break
[4] SCI status check and receive data read:
[5] Serial reception continuation procedure:
Notes: 1. Supported only by the H8S/2239
The RxD pin is automatically
designated as the receive data input
pin.
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
The RDRF flag is cleared automatically
when the DMAC *
activated by an RXI interrupt and the
RDR value is read.
2. The case, in which the DTC
Group.
automatically clears the RDRF
flag, occurs only when DISEL in
DTC is 0 with the transfer counter
not being 0. Therefore, the RDRF
flag should be cleared by CPU
when DISEL is 1, or when DISEL
is 0 with the transfer counter
being 0.
1
or the DTC *
2
is
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