D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 818

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
6. The operating frequency and user branch destination are set to the FPEFEQ and FUBRA
7. Initialization
8. The return value in the initialization program, FPFR (general register R0L) is determined.
Rev.6.00 Mar. 18, 2009 Page 758 of 980
REJ09B0050-0600
⎯ If the value of the DPFR parameter is different from before downloading, check the SS bit
parameters for initialization.
⎯ The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
⎯ Set the user branch destination address as the FUBRA parameter (general register ER1)
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the
start address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called
and initialization is executed by using the following steps.
MOV.L
JSR
NOP
⎯ The general registers other than ER0, ER1 are held in the initialization program.
⎯ R0L is a return value of the FPFR parameter.
⎯ Since the stack area is used in the initialization program, a stack area of a maximum 128
⎯ Interrupts can be accepted during the execution of the initialization program. The program
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
ER0).
The allowable setting range for the FPEFEQ parameter is 8 MHz to 34 MHz. When the
frequency is set to out of this range, an error is returned to the FPFR parameter of the
initialization program and initialization is not performed. For details on the frequency
setting, see the description in 20.3.2 (2) (a), Flash programming/erasing frequency
parameter (FPEFEQ: general register ER0 of CPU).
and the user branch enable bits (FUBE15 to FUBE0) as the FPEFEQ parameter (general
register ER0). Set FUBRA and FUBE15 to FUBE0 to 0 if the user branch function is not
required.
Do use programmable user MAT as the user branch destination. Also, do not use an area
containing a downloaded internal program as the user branch destination. After user branch
processing completes, use the RTS instruction to return to programming processing.
For details, see the descriptions in 21.3.2 (2) (a), Flash programming/erasing frequency
parameter (FPEFEQ: general register ER0 of CPU), and 21.3.2 (2) (b), Flash user branch
address setting parameter (FUBRA: general register ER1 of CPU).
bytes must be allocated in RAM.
storage area and stack area in the on-chip RAM and register values must not be destroyed.
DLTOP+32,ER2;
@ER2;
Set entry address to ER2
Call initialization routine