D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 796
D12363VTE33
Manufacturer Part Number
D12363VTE33
Description
MCU 3V 0K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2368VTE34V.pdf
(1044 pages)
Specifications of D12363VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412363VTE33
HD6412363VTE33
HD6412363VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12363VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Table 20.4 Parameters and Target Modes
Name of
Parameter
Download pass
and fail result
Flash pass and fail
result
Flash
programming/
erasing frequency
control
Flash user branch
address set
Flash multipurpose
address area
Flash multipurpose
data destination
area
Flash erase block
select
Note:
(1)
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the 128-kbyte area starting from the address specified by FTDAR.
Download control is set in the program/erase interface register, and the return value is passed
using the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by writing the single byte of
the start address specified by FTDAR to the value other than the return value of download (for
example, H'FF) before the download start (before setting the SCO bit to 1).
Rev.6.00 Mar. 18, 2009 Page 736 of 980
REJ09B0050-0600
Download Control
*
A single byte of the start address to download an on-chip program, which is specified by
FTDAR.
Abbrevia-
tion
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
Down
Load
⎯
⎯
⎯
⎯
⎯
Initializa-
tion
⎯
⎯
⎯
⎯
Program-
ming
⎯
⎯
⎯
⎯
Erasure
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Alloca-
tion
On-chip
RAM*
R0L of
CPU
ER0 of
CPU
ER1 of
CPU
ER1 of
CPU
ER0 of
CPU
R0L of
CPU
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