D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 492

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.4
TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has
six TIER registers, one for each channel.
Rev.6.00 Mar. 18, 2009 Page 432 of 980
REJ09B0050-0600
Bit
7
6
5
4
3
Bit Name
TTGE
–
TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
Initial value
0
1
0
0
0
R/W
R/W
–
R/W
R/W
R/W
Description
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1 and cannot be modified.
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled