HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 615
![MCU 5V 0K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD6413008VX25
Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VX25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
HD6413008VTE25
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8TCSR0—Timer Control/Status Register 0
Note: 1. Only 0 can be written to bits 7 to 5 to clear these flags.
Initial value
Read/Write
Bit
Compare match/input capture flag B
0
1
R/(W)
CMFB
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
• 8TCNT = TCORB
• The 8TCNT value is transferred to TCORB by an input capture signal when
7
0
TCORB functions as an input capture register.
*
Compare match flag A
1
0
1
R/(W)
CMFA
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
8TCNT = TCORA
6
0
*
Timer overflow flag
1
0
1
R/(W)
OVF
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
8TCNT overflows from H'FF to H'00.
5
0
Note: 2. TRGE is bit 7 of the A/D control register (ADCR).
*
TRGE *
1
A/D trigger enable
0
1
ADTE
R/W
2
4
0
ADTE
Bit 4
0
1
0
1
Output/input capture edge select B3 and B2
8TCSR1
ICE in
A/D converter start requests by compare match
A or an external trigger are disabled
A/D converter start requests by compare match
A or an external trigger are disabled
A/D converter start requests by an external trigger are enabled, and
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and
A/D converter start requests by an external trigger are disabled
OIS3
0
1
R/W
3
0
Bit 3
OIS3
0
1
0
1
Bit 1
Output select A1 and A0
OS1
OIS2
0
1
R/W
2
0
Bit 2
OIS2
Rev.4.00 Aug. 20, 2007 Page 569 of 638
Bit 0
OS0
0
1
0
1
0
1
0
1
Description
0
1
0
1
H'FFF82
No change at compare match B
0 output at compare match B
1 output at compare match B
Output toggles at compare match
B
TCORB input capture on rising
edge
TCORB input capture on falling
edge
TCORB input capture on both
rising and falling edges
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
OS1
R/W
1
0
Appendix B Internal I/O Registers
Description
Description
OS0
R/W
0
0
8-bit timer channel 0
REJ09B0395-0400
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