HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 158
![MCU 5V 0K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD6413008VX25
Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VX25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
HD6413008VTE25
- Current page: 158 of 688
- Download datasheet (4Mb)
6. Bus Controller
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, selects the extended memory map, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
0
1
Bits 5 to 3—Reserved (must not be set to 1): These bits can be read and written, but must not be
set to 1. Normal operation cannot be guaranteed if 1 is written in these bits.
Bit 2— Reserved (must not be set to 0): This bit can be read and written, but must not be set to
0. Normal operation cannot be guaranteed if 0 is written in this bit.
Rev.4.00 Aug. 20, 2007 Page 112 of 638
REJ09B0395-0400
Description
No idle cycle inserted in case of consecutive external read cycles for different
areas
Idle cycle inserted in case of consecutive external read cycles for different
areas
Description
No idle cycle inserted in case of consecutive external read and write cycles
Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
(Initial value)
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