HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 337
![MCU 5V 0K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD6413008VX25
Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VX25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
HD6413008VTE25
- Current page: 337 of 688
- Download datasheet (4Mb)
10.2.6
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Address H'FFFA6
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register B (NDRB)
15
NDR15
to TP
R/W
7
0
⎯
⎯
7
1
8
). During TPC output, when an 16-bit timer compare match event
Next data 15 to 12
These bits store the next output
data for TPC output group 3
NDR14
R/W
6
0
⎯
⎯
6
1
NDR13
R/W
5
0
⎯
⎯
5
1
10. Programmable Timing Pattern Controller (TPC)
NDR12
R/W
Reserved bits
4
0
⎯
⎯
4
1
Rev.4.00 Aug. 20, 2007 Page 291 of 638
NDR11
R/W
3
0
⎯
⎯
3
1
Next data 11 to 8
These bits store the next output
data for TPC output group 2
NDR10
R/W
2
0
⎯
⎯
2
1
NDR9
R/W
REJ09B0395-0400
1
0
⎯
⎯
1
1
NDR8
R/W
0
0
⎯
⎯
0
1
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