HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 141
![MCU 5V 0K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD6413008VX25
Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VX25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
HD6413008VTE25
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Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
• The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
• In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is
• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
interrupt request is sent to the interrupt controller.
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only interrupts with priority level 1 are accepted; interrupt requests
with priority level 0 are held pending. If the I bit and UI bit are both set to 1, all other interrupt
requests are held pending.
current instruction has been completed.
saved indicates the address of the first instruction that will be executed after the return from the
interrupt service routine.
starts executing from the address indicated by the contents of the vector address.
a.
All interrupts are
unmasked
Figure 5.5 Interrupt Masking State Transitions (Example)
I
←
0
Exception handling,
or I
←
1, UI
c.
All interrupts are
masked except NMI
←
I
1
←
I
←
1, UI
0
←
0
Rev.4.00 Aug. 20, 2007 Page 95 of 638
UI
←
0
b.
Only NMI, IRQ , and
IRQ are unmasked
Exception handling,
or UI
3
5. Interrupt Controller
←
1
REJ09B0395-0400
2
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