HD6413008VX25 Renesas Electronics America, HD6413008VX25 Datasheet - Page 25
![MCU 5V 0K 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
HD6413008VX25
Manufacturer Part Number
HD6413008VX25
Description
MCU 5V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13008VFBL25V.pdf
(688 pages)
Specifications of HD6413008VX25
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6413008VTE25
HD6413008VTE25
HD6413008VTE25
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10.2 Register Descriptions ........................................................................................................ 287
10.3 Operation........................................................................................................................... 300
10.4 Usage Notes ...................................................................................................................... 307
Section 11 Watchdog Timer
11.1 Overview........................................................................................................................... 309
11.2 Register Descriptions ........................................................................................................ 311
11.3 Operation........................................................................................................................... 317
11.4 Interrupts ........................................................................................................................... 320
11.5 Usage Notes ...................................................................................................................... 320
10.2.1 Port A Data Direction Register (PADDR) ........................................................... 287
10.2.2 Port A Data Register (PADR) .............................................................................. 287
10.2.3 Port B Data Direction Register (PBDDR)............................................................ 288
10.2.4 Port B Data Register (PBDR) .............................................................................. 288
10.2.5 Next Data Register A (NDRA) ............................................................................ 289
10.2.6 Next Data Register B (NDRB)............................................................................. 291
10.2.7 Next Data Enable Register A (NDERA).............................................................. 293
10.2.8 Next Data Enable Register B (NDERB) .............................................................. 294
10.2.9 TPC Output Control Register (TPCR) ................................................................. 295
10.2.10 TPC Output Mode Register (TPMR) ................................................................... 298
10.3.1 Overview.............................................................................................................. 300
10.3.2 Output Timing...................................................................................................... 301
10.3.3 Normal TPC Output............................................................................................. 302
10.3.4 Non-Overlapping TPC Output ............................................................................. 304
10.3.5 TPC Output Triggering by Input Capture ............................................................ 306
10.4.1 Operation of TPC Output Pins ............................................................................. 307
10.4.2 Note on Non-Overlapping Output........................................................................ 307
11.1.1 Features................................................................................................................ 309
11.1.2 Block Diagram ..................................................................................................... 310
11.1.3 Pin Configuration................................................................................................. 310
11.1.4 Register Configuration......................................................................................... 311
11.2.1 Timer Counter (TCNT)........................................................................................ 311
11.2.2 Timer Control/Status Register (TCSR) ................................................................ 312
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 314
11.2.4 Notes on Register Access..................................................................................... 315
11.3.1 Watchdog Timer Operation ................................................................................. 317
11.3.2 Interval Timer Operation ..................................................................................... 318
11.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 318
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 319
............................................................................................. 309
Rev.4.00 Aug. 20, 2007, Page xxiii of xliv
REJ09B0395-0400
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