HD64F3642AH Renesas Electronics America, HD64F3642AH Datasheet - Page 75
HD64F3642AH
Manufacturer Part Number
HD64F3642AH
Description
IC H8 MCU FLASH 16K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3642AH
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Example 2: BSET instruction executed designating port 3
P3
signal at P3
example, the BSET instruction is used to change pin P3
[A: Prior to executing BSET]
[B: BSET instruction executed]
[C: After executing BSET]
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3
P3
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
Input/output
Pin state
PCR3
PDR3
Input/output
Pin state
PCR3
PDR3
BSET
7
5
and P3
to P3
7
0
and P3
are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
6
6
#0
are designated as input pins, with a low-level signal input at P3
. The remaining pins, P3
,
6
P3
Input
Low
level
0
1
P3
Input
Low
level
0
0
are input pins, the CPU reads the pin states (low-level and high-level input).
7
7
@PDR3
P3
Input
High
level
0
0
P3
Input
High
level
0
1
6
6
5
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
to P3
The BSET instruction is executed designating port 3.
5
5
0
, are output pins and output low-level signals. In this
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
4
4
0
to high-level output.
Rev. 6.00 Sep 12, 2006 page 53 of 526
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
3
3
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
2
2
7
and a high-level
P3
Output
Low
level
1
0
P3
Output
Low
level
1
0
REJ09B0326-0600
1
1
Section 2 CPU
P3
Output
Low
level
1
0
P3
Output
High
level
1
1
0
0
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