HD64F3642AH Renesas Electronics America, HD64F3642AH Datasheet - Page 121
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HD64F3642AH
Manufacturer Part Number
HD64F3642AH
Description
IC H8 MCU FLASH 16K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3642AH
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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5.6.3
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are
5.7
5.7.1
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ
IRQ
active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
5.7.2
Active (medium-speed) mode is cleared by a SLEEP instruction or by input at the RES pin.
5.7.3
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep (high-speed) mode is entered if MSON is cleared to 0 in SYSCR2, and sleep (medium-
speed) mode is entered if MSON is set to 1. Direct transfer to active (high-speed) mode or to
subactive mode is also possible. See section 5.8, Direct Transfer, below for details.
Clearing by RES pin
When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is
cleared.
0
W
interrupts in watch mode, or any interrupt in sleep (medium-speed) mode. A transition to
/2,
Active (Medium-Speed) Mode
Transition to Active (Medium-Speed) Mode
Clearing Active (Medium-Speed) Mode
Operating Frequency in Subactive Mode
Operating Frequency in Active (Medium-Speed) Mode
W
/4, and
W
/8.
0
or IRQ
1
Rev. 6.00 Sep 12, 2006 page 99 of 526
interrupts in standby mode, timer A or
Section 5 Power-Down Modes
REJ09B0326-0600
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