HD64F3687GH Renesas Electronics America, HD64F3687GH Datasheet - Page 527
HD64F3687GH
Manufacturer Part Number
HD64F3687GH
Description
IC H8 MCU FLASH 56K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GH
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Item
13.4.9 Timer Z Output
Timing
Figure 13.44 Example of
Output Disable Timing of
Timer Z by Writing to
TOER
Figure 13.45 Example of
Output Disable Timing of
Timer Z by External
Trigger
Section 14 Watchdog
Timer
14.2.1 Timer
Control/Status Register
WD (TCSRWD)
Section 17 I
Interface 2 (IIC2)
17.3.5 I
Register (ICSR)
17.7 Usage Notes
Section 18 A/D Converter
18.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
2
C Bus Status
2
C Bus
252
314
336
340
Page Revision (See Manual for Details)
238
238
Added
Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
Timer Z
output pin
TOER
Bit
4
Bit
3
Address bus
Timer Z
output pin
Bit Name
TCSRWE
Bit Name
STOP
Timer Z output
Timer Z output
N
Timer output
Timer Z output
Description
Timer Control/Status Register WD Write
Enable
Description
Stop Condition Detection Flag
[Setting conditions]
TOER address
T
1
In master mode, when a stop condition is
detected after frame transfer
In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
Rev.5.00 Nov. 02, 2005 Page 493 of 500
I/O port
T
2
I/O port
H'FF
I/O port
I/O port
REJ09B0027-0500
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