HD64F3687GH Renesas Electronics America, HD64F3687GH Datasheet - Page 24
HD64F3687GH
Manufacturer Part Number
HD64F3687GH
Description
IC H8 MCU FLASH 56K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GH
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71
Figure 5.6 Example of External Clock Input ................................................................................ 71
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73
Figure 5.11 Example of Incorrect Board Design .......................................................................... 74
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 81
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 90
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 99
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 101
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 104
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 109
Figure 9.2 Port 2 Pin Configuration............................................................................................ 115
Figure 9.3 Port 3 Pin Configuration............................................................................................ 119
Figure 9.4 Port 5 Pin Configuration............................................................................................ 122
Figure 9.5 Port 6 Pin Configuration............................................................................................ 128
Figure 9.6 Port 7 Pin Configuration............................................................................................ 134
Figure 9.7 Port 8 Pin Configuration............................................................................................ 137
Figure 9.8 Port B Pin Configuration........................................................................................... 139
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 142
Figure 10.2 Definition of Time Expression ................................................................................ 147
Figure 10.3 Initial Setting Procedure.......................................................................................... 150
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 151
Section 11 Timer B1
Figure 11.1 Block Diagram of Timer B1.................................................................................... 153
Section 12 Timer V
Figure 12.1 Block Diagram of Timer V ..................................................................................... 160
Rev.5.00 Nov. 02, 2005 Page xxii of xxxii
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