HD64F3687GH Renesas Electronics America, HD64F3687GH Datasheet - Page 385
HD64F3687GH
Manufacturer Part Number
HD64F3687GH
Description
IC H8 MCU FLASH 56K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GH
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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19.2
Pins used in the EEPROM are listed in table 19.1.
Table 19.1 Pin Configuration
19.3
The EEPROM has a following register.
19.3.1
EKR is an 8-bit readable/writable register, which changes the slave address code written in the
EEPROM. The slave address code is changed by writing H'5F in EKR and then writing either of
H'00 to H'07 as an address code to the H'FF09 address in the EEPROM by the byte write method.
EKR is initialized to H'FF.
Pin name
Serial clock pin
Serial data pin
EEPROM key register (EKR)
Input/Output Pins
Register Description
EEPROM Key Register (EKR)
SCL
SDA
Symbol
Input
Input/Output
Input/Output Function
The SCL pin is used to control serial input/output data
timing. The data is input at the rising edge of the
clock and output at the falling edge of the clock. The
SCL pin needs to be pulled up by resistor as that pin
is open-drain driven structure of the I
proper resistor value for your system by considering
V
DC Characteristics and in section 23.2.3, AC
Characteristics. Maximum clock frequency is 400
kHz.
The SDA pin is bidirectional for serial data transfer.
The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor
value for your system by considering V
C
Characteristics and in section 23.2.3, AC
Characteristics. Except for a start condition and a
stop condition which will be discussed later, the high-
to-low and low-to-high change of SDA input should be
done during SCL low periods.
OL
IN
, I
pin capacitance in section 23.2.2, DC
OL
, and the C
Rev.5.00 Nov. 02, 2005 Page 351 of 500
IN
pin capacitance in section 23.2.2,
Section 19 EEPROM
2
C pin. Use
REJ09B0027-0500
OL
, I
OL
, and the
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