HD64F3687GH Renesas Electronics America, HD64F3687GH Datasheet - Page 233
HD64F3687GH
Manufacturer Part Number
HD64F3687GH
Description
IC H8 MCU FLASH 56K 64-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3684GFPV.pdf
(538 pages)
Specifications of HD64F3687GH
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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13.4
13.4.1
When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding
channel begins counting. TCNT can operate as a free-running counter, periodic counter, for
example. Figure 13.7 shows an example of the counter operation setting procedure.
1. Free-running count operation and periodic count operation
Select output compare register
Select counter clearing source
Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as free-
running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter
starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag
in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point,
timer Z requests an interrupt. After overflow, TCNT starts an increment operation again from
H'0000.
Start count operation
Select counter clock
Operation selection
Periodic counter
Operation
Counter Operation
Set period
Figure 13.7 Example of Counter Operation Setting Procedure
[1]
[4]
[2]
[3]
[5]
Free-running counter
Rev.5.00 Nov. 02, 2005 Page 199 of 500
[1] Select the counter
[2] For periodic counter
[3] Designate the general
[4] Set the periodic counter
[5] Set the STR bit in TSTR
clock with bits
TPSC2 to TPSC0 in
TCR. When an external
clock is selected, select
the external clock edge
with bits CKEG1
and CKEG0 in TCR.
operation, select the
TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
register selected in [2]
as an output compare
register by means of
TIOR.
cycle in the general
register selected
in [2].
to 1 to start the counter
operation.
Section 13 Timer Z
REJ09B0027-0500
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