HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 253

IC H8 MCU FLASH 8K 32-QFP

HD64F36912GFH

Manufacturer Part Number
HD64F36912GFH
Description
IC H8 MCU FLASH 8K 32-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F36912GFH

Core Processor
H8/300H
Core Size
16-Bit
Speed
12MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F36912GFH
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.5.4
Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, SCI3 operates as described below.
1. SCI3 performs internal initialization synchronous with a synchronization clock input or
2. SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
RDRF
OER
LSI
operation
User
processing
Serial
clock
Serial
data
output, starts receiving data.
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode
RXI interrupt
request
generated
Bit 7
Bit 0
RDRF flag
cleared
to 0
RDR data read
1 frame
Bit 7
RXI interrupt request generated
Bit 0
Section 14 Serial Communication Interface 3 (SCI3)
Bit 1
Rev. 3.00 Sep. 14, 2006 Page 223 of 408
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
Bit 7
ERI interrupt request
generated by
overrun error
Overrun error
processing
REJ09B0105-0300

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