HD64F36912GFH Renesas Electronics America, HD64F36912GFH Datasheet - Page 123

• Manufacturer Part Number: HD64F36912GFH
• Description: IC H8 MCU FLASH 8K 32-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F36912GFH

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.2.1
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an
interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling. Sleep
mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested
interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in sleep mode, the
CPU goes into the reset state and sleep mode is cleared.
6.2.2
In standby mode, the system clock oscillator is halted, and operation of the CPU and on-chip
peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be retained as long as the voltage set by the RAM data retention voltage is
provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the on-chip oscillator
starts functioning. The external oscillator also starts functioning when used. After the time set by
the STS2 to STS0 bits in SYSCR1 has elapsed, standby mode is cleared and the CPU starts
interrupt exception handling. Standby mode is not cleared if the I bit in the condition code register
(CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.
When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. The
system clock is supplied to the entire chip as soon as the on-chip oscillator starts functioning. The
RES pin must be kept low for the rated period. On driving the RES pin high, after the oscillation
stabilization time set by the power-on reset circuit has elapsed, the internal reset signal is cleared
and the CPU starts reset exception handling.
Sleep Mode
Standby Mode
Rev. 3.00 Sep. 14, 2006 Page 93 of 408
Section 6 Power-Down Modes
REJ09B0105-0300