MC9S08RG60CFGE Freescale Semiconductor, MC9S08RG60CFGE Datasheet - Page 110
MC9S08RG60CFGE
Manufacturer Part Number
MC9S08RG60CFGE
Description
IC MCU 60K FLASH 8MHZ 44LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08RE8FJE.pdf
(234 pages)
Specifications of MC9S08RG60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08RG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
- 40 C
Controller Family/series
HCS08
No. Of I/o's
39
Ram Memory Size
60KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
For Use With
DEMO9S08RG60E - BOARD DEMO S08RG/RC/RD/RE FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC9S08RG60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
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Carrier Modulator Transmitter (CMT) Block Description
8.5.1
The carrier signal is generated by counting a register-selected number of input clocks (125 ns for an 8 MHz
bus) for both the carrier high time and the carrier low time. The period is determined by the total number
of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted.
The high and low time values are user programmable and are held in two registers.
An alternate set of high/low count values is held in another set of registers to allow the generation of dual
frequency FSK (frequency shift keying) protocols without CPU intervention.
The MCGEN bit in the CMTMSC register must be set and the BASE bit must be cleared to enable carrier
generator clocks. When the BASE bit is set, the carrier output to the modulator is held high continuously.
The block diagram is shown in
110
1. To prevent spurious operation, initialize all data and control registers before beginning a transmission (MCGEN=1).
2. These bits are not double buffered and should not be changed during a transmission (while MCGEN=1).
Baseband
IRO Latch
Extended
Space
Mode
Time
FSK
Carrier Generator
MCGEN
if any of the count values are equal to zero.
Only non-zero data values are allowed. The carrier generator will not work
Bit
1
1
1
1
0
(1)
BASE
Bit
0
1
0
x
x
(2)
Figure
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Bit
FSK
Table 8-2. CMT Modes of Operation
0
x
1
x
x
(2)
8-3.
EXSPC
Bit
0
0
0
1
x
NOTE
f
f
f
f
secondary high/low registers.
f
Setting the EXSPC bit causes subsequent modulator cycles
to be spaces (modulator out not asserted) for the duration of
the modulator period (mark and space times).
IROL bit controls state of IRO pin.
CG
CG
CG
CG
CG
control alternates between primary high/low registers and
controlled by primary high and low registers.
transmitted to IRO pin when modulator gate is open.
is always high. IRO pin high when modulator gate is open.
transmitted to IRO pin when modulator gate is open.
Comment
Freescale Semiconductor
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