MC908GR32AVFAE Freescale Semiconductor, MC908GR32AVFAE Datasheet - Page 258
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MC908GR32AVFAE
Manufacturer Part Number
MC908GR32AVFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Interface Module (TIM2)
CHxMAX — Channel x Maximum Duty Cycle Bit
18.8.5 TIM2 Channel Registers
These read/write registers contain the captured TIM2 counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM2 channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM2 channel x registers
(T2CHxH) inhibits input captures until the low byte (T2CHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM2 channel x registers
(T2CHxH) inhibits output compares until the low byte (T2CHxL) is written.
258
When the TOVx bit is at a 1 and clear output on compare is selected, setting the CHxMAX bit forces
the duty cycle of buffered and unbuffered PWM signals to 100%. As
bit takes effect in the cycle after it is set or cleared. The output stays at 100% duty cycle level until the
cycle after CHxMAX is cleared.
Figure 18-10. TIM2 Channel Registers (T2CH0H/L:T2CH5H/L) (Sheet 1 of 3)
PTDx/T2CHx
Address: $0031
Address: $0032
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
CHxMAX
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
OVERFLOW
Bit 15
Bit 7
Bit 7
Bit 7
COMPARE
T2CH0H
T2CH0L
PERIOD
OUTPUT
Bit 14
Bit 6
6
6
Figure 18-9. CHxMAX Latency
OVERFLOW
Bit 13
Bit 5
5
5
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
NOTE
Bit 12
Bit 4
OVERFLOW
4
4
Bit 11
Bit 3
COMPARE
OUTPUT
3
3
OVERFLOW
Bit 10
Bit 2
2
2
Figure 18-9
COMPARE
OUTPUT
Bit 9
Bit 1
1
1
OVERFLOW
shows, the CHxMAX
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
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