MC908GR32AVFAE Freescale Semiconductor, MC908GR32AVFAE Datasheet - Page 183
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MC908GR32AVFAE
Manufacturer Part Number
MC908GR32AVFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14
System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit
(CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in
Figure
controller that coordinates CPU and exception timing.
The SIM is responsible for:
Table 14-1
Freescale Semiconductor
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt arbitration
14-1.
Stop/wait/reset/break entry and recovery
Internal clock control
shows the internal signal names used in this section.
Table 14-1
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
PORRST
IRST
R/W
IAB
IDB
is a summary of the SIM input/output (I/O) registers. The SIM is a system state
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 14-1. Signal Name Conventions
Description
183
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