MC908GR32ACFAER Freescale Semiconductor, MC908GR32ACFAER Datasheet - Page 285

• Manufacturer Part Number: MC908GR32ACFAER
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32ACFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.9.3 CGM Acquisition/Lock Time Information
Freescale Semiconductor
Acquisition mode entry frequency tolerance
Tracking mode entry frequency tolerance
LOCK entry frequency tolerance
LOCK exit frequency tolerance
Reference cycles per acquisition mode period
Reference cycles per tracking mode period
Automatic mode time to stable
Automatic stable to lock time
Automatic lock time (t
PLL jitter, deviation of average bus frequency
1. Deviation between VCO frequency and desired frequency to enter PLL acquisition mode.
2. Deviation between VCO frequency and desired frequency to enter PLL tracking mode (stable).
3. Deviation between VCO frequency and desired frequency to enter locked mode.
4. Deviation between VCO frequency and desired frequency to exit locked mode.
5. Acquisition time is an integer multiple of reference cycles divided by reference clock.
6. Stable to lock time is an integer multiple of reference cycles divided by reference clock.
7. Maximum lock time depends on CGMXFC filter components, power supply filtering, and reference clock stability. PLL may
over 2 ms period
not lock if improper components or poor filtering and layout are used.
Characteristic
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
ACQ
+ t
AL
(4)
)
(7)
(3)
(2)
(1)
Symbol
Δ
t
Δ
n
Δ
Δ
n
t
LOCK
LOCK
ACQ
t
ACQ
ACQ
TRK
UNL
TRK
AL
f
J
n
n
ACQ
TRK
± 0.9
± 3.6
Clock Generation Module (CGM) Characteristics
Min
—
—
—
0
0
/f
0
/f
RCLK
RCLK
See note
See note
Typ
128
—
—
—
—
32
—
5
(5)
(6)
0.025% x
f
RCLK
± 7.2
± 3.6
± 0.9
± 1.8
Max
N/4
25
—
—
—
—
x
Unit
ms
Hz
%
%
%
%
s
s
285