MC908GR32ACFAER Freescale Semiconductor, MC908GR32ACFAER Datasheet - Page 233

• Manufacturer Part Number: MC908GR32ACFAER
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32ACFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

If TIM1 functions are not required during wait mode, reduce power consumption by stopping the TIM1
before executing the WAIT instruction.
17.6 TIM1 During Break Interrupts
A break interrupt stops the TIM1 counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
17.7 Input/Output Signals
Port D shares two of its pins with the TIM1. The two TIM1 channel I/O pins are PTD4/T1CH0 and
PTD5/T1CH1.
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTD4/T1CH0 can be configured as a buffered output compare or buffered PWM pin.
17.8 Input/Output Registers
The following I/O registers control and monitor operation of the TIM:
17.8.1 TIM1 Status and Control Register
The TIM1 status and control register (T1SC) does the following:
Freescale Semiconductor
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TIM1 status and control register (T1SC)
TIM1 counter registers (T1CNTH:T1CNTL)
TIM1 counter modulo registers (T1MODH:T1MODL)
TIM1 channel status and control registers (T1SC0 and T1SC1)
TIM1 channel registers (T1CH0H:T1CH0L and T1CH1H:T1CH1L)
Enables TIM1 overflow interrupts
Flags TIM1 overflows
Stops the TIM1 counter
Resets the TIM1 counter
Prescales the TIM1 counter clock
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Figure 14-21. Break Status Register
(BSR).
TIM1 During Break Interrupts
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