MC908GR32ACFAER Freescale Semiconductor, MC908GR32ACFAER Datasheet - Page 249
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/39/61/396123/4734654_sml.jpg)
MC908GR32ACFAER
Manufacturer Part Number
MC908GR32ACFAER
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32ACFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32ACFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the T2CH0
pin. The TIM2 channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM2 channel 0 status and control register (T2SC0) links channel 0 and channel 1.
The TIM2 channel 0 registers initially control the pulse width on the T2CH0 pin. Writing to the TIM2
channel 1 registers enables the TIM2 channel 1 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM2 channel registers (0 or 1) that
control the pulse width are the ones written to last. T2SC0 controls and monitors the buffered PWM
function, and TIM2 channel 1 status and control register (T2SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T2CH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the T2CH2
pin. The TIM2 channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIM2 channel 2 status and control register (T2SC2) links channel 2 and channel 3.
The TIM2 channel 2 registers initially control the pulse width on the T2CH2 pin. Writing to the TIM2
channel 3 registers enables the TIM2 channel 3 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM2 channel registers (2 or 3) that
control the pulse width are the ones written to last. T2SC2 controls and monitors the buffered PWM
function, and TIM2 channel 3 status and control register (T2SC3) is unused. While the MS2B bit is set,
the channel 3 pin, T2CH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the T2CH4
pin. The TIM2 channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS4B bit in TIM2 channel 4 status and control register (T2SC4) links channel 4 and channel 5.
The TIM2 channel 4 registers initially control the pulse width on the T2CH4 pin. Writing to the TIM2
channel 5 registers enables the TIM2 channel 5 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM2 channel registers (4 or 5) that
control the pulse width are the ones written to last. T2SC4 controls and monitors the buffered PWM
function, and TIM2 channel 5 status and control register (T2SC5) is unused. While the MS4B bit is set,
the channel 5 pin, T2CH5, is available as a general-purpose I/O pin.
Freescale Semiconductor
•
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable TIM2 overflow interrupts and write the new value
in the TIM2 overflow interrupt routine. The TIM2 overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
NOTE
Functional Description
249
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