MC908GR32ACFAER Freescale Semiconductor, MC908GR32ACFAER Datasheet - Page 150
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/39/61/396123/4734654_sml.jpg)
MC908GR32ACFAER
Manufacturer Part Number
MC908GR32ACFAER
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32ACFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32ACFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Input/Output (I/O) Ports
12.9.2 Data Direction Register G
Data direction register G (DDRG) determines whether each port G pin is an input or an output. Writing a 1
to a DDRG bit enables the output buffer for the corresponding port G pin; a 0 disables the output buffer.
DDRG7–DDRG0 — Data Direction Register G Bits
Figure 12-25
When bit DDRGx is a 1, reading address $0441 reads the PTGx data latch. When bit DDRGx is a 0,
reading address $0441 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
150
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
These read/write bits control port G data direction. Reset clears DDRG7–DDRG0], configuring all port
G pins as inputs.
DDRG
Bit
0
1
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
Address:
shows the port G I/O logic.
PTG
X
Bit
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Reset:
Read:
X
Write:
(1)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
READ DDRG ($0445)
WRITE DDRG ($0445)
WRITE PTG ($0441)
READ PTG ($0441)
DDRG7
$0445
Bit 7
0
Input, Hi-Z
Figure 12-24. Data Direction Register G (DDRG)
I/O Pin
Output
Mode
DDRG6
6
0
(2)
Table 12-8. Port G Pin Functions
RESET
Figure 12-25. Port G I/O Circuit
DDRG5
5
0
Accesses to DDRG
DDRG7–DDRG0
DDRG7–DDRG0
Table 12-8
Read/Write
DDRG4
NOTE
DDRGx
PTGx
4
0
DDRG3
summarizes the operation of the port G pins.
3
0
DDRG2
PTG7–PTG0
2
0
Read
Pin
DDRG1
Accesses to PTG
1
0
Freescale Semiconductor
DDRG0
Bit 0
PTGx
0
PTG7–PTG0
PTG7–PTG0
Write
(3)
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