MC908LJ12CFBE Freescale Semiconductor, MC908LJ12CFBE Datasheet - Page 380

• Manufacturer Part Number: MC908LJ12CFBE
• Description: IC MCU 12K FLASH 8MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 20
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 20
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Voltage Inhibit (LVI)
21.4.1 Interrupt LVI Operation
21.4.2 Forced Reset Operation
21.4.3 Voltage Hysteresis Protection
Technical Data
380
In applications that can operate at V
software can monitor V
interrupt enable bit, LVIIE, to enable interrupt requests. In the
configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0
to enable the LVI module, and the LVIRSTD bit must be at logic 1 to
disable LVI resets.
The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes
state (toggles). When LVIF is set, a CPU interrupt request is generated
if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF bit
can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit,
LVIIAK.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls below the V
the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI
module and to enable LVI resets.
If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI
reset has a higher priority over LVI interrupt. In this case, when V
below the V
cleared.
Once the LVI has triggered (by having V
will maintain a reset condition until V
voltage, V
continually entering and exiting reset if V
V
TRIPF
. V
TRIPR
TRIPR
TRIPF
Low-Voltage Inhibit (LVI)
. This prevents a condition in which the MCU is
is greater than V
TRIPF
level, an LVI reset will occur, and the LVIIE bit will be
level. In the configuration register 1 (CONFIG1),
DD
by polling the LVIOUT bit, or by setting the LVI
DD
to remain above the V
TRIPF
DD
DD
by the hysteresis voltage, V
levels below the V
rises above the rising trip point
DD
DD
fall below V
is approximately equal to
MC68HC908LJ12
Freescale Semiconductor
TRIPF
TRIPF
TRIPF
level,
), the LVI
—
level,
DD
Rev. 2.1
HYS
falls
DD
.