MC908LJ12CFBE Freescale Semiconductor, MC908LJ12CFBE Datasheet - Page 314
![IC MCU 12K FLASH 8MHZ 52-LQFP](/photos/12/35/123587/mc908lj12cfbe_sml.jpg)
MC908LJ12CFBE
Manufacturer Part Number
MC908LJ12CFBE
Description
IC MCU 12K FLASH 8MHZ 52-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC98LJ12CFUE.pdf
(414 pages)
Specifications of MC908LJ12CFBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
20
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-LQFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
20
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908LJ12CFBE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC908LJ12CFBE
Manufacturer:
SANYO
Quantity:
650
Company:
Part Number:
MC908LJ12CFBE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908LJ12CFBE
Manufacturer:
FREESCALE
Quantity:
20 000
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Analog-to-Digital Converter (ADC)
15.8.3 ADC Clock Control Register
Technical Data
314
Address:
The ADC clock control register (ADCLK) selects the clock frequency for
the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Reset:
Read:
Write:
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 15-2
should be set to between 32kHz and 2MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
Figure 15-9. ADC Clock Control Register (ADICLK)
ADIV2
$003F
ADIV2
X = don’t care
Analog-to-Digital Converter (ADC)
0
0
0
0
0
1
shows the available clock configurations. The ADC clock
= Unimplemented
ADIV1
Table 15-2. ADC Clock Divide Ratio
0
ADIV1
X
0
0
1
1
ADIV0
0
ADIV0
X
0
1
0
1
ADICLK
0
MODE1
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
R
0
ADC Clock Rate
MC68HC908LJ12
= Reserved
MODE0
Freescale Semiconductor
1
0
0
—
Rev. 2.1
R
0
0
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