MCF52110CVM80J Freescale Semiconductor, MCF52110CVM80J Datasheet - Page 24

• Manufacturer Part Number: MCF52110CVM80J
• Description: IC MCU 128K FLASH 80MHZ 81MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xxr

Specifications of MCF52110CVM80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1.15
Table 17
Freescale Semiconductor
Processor Status Clock
All Processor Status
Development Serial
Development Serial
Processor Status
contains a list of EzPort external signals.
Signal Name
Debug Data
EzPort Signal Descriptions
Outputs
Outputs
Output
Input
EzPort Serial Data Out
EzPort Serial Data In
EzPort Chip Select
Signal Name
EzPort Clock
Abbreviation
DDATA[3:0]
PSTCLK
PST[3:0]
ALLPST
DSO
DSI
Table 16. Debug Support Signals (continued)
MCF52110 ColdFire Microcontroller, Rev. 1
Table 17. EzPort Signal Descriptions
Abbreviation
Development Serial Input - Internally synchronized input that provides
data input for the serial communication port to the debug module, after
the DSCLK has been seen as high (logic 1).
Development Serial Output - Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
Logical AND of PST[3:0]. The CLKOUT signal can be used by the
development system to know when to sample ALLPST.
EZPCK
EZPCS
EZPD
EZPQ
Shift clock for EzPort transfers.
Chip select for signalling the start and end of
serial transfers.
EZPD is sampled on the rising edge of
EZPCK.
EZPQ transitions on the falling edge of
EZPCK.
Function
Function
Family Configurations
I/O
O
I
I
I
I/O
O
O
O
O
O
I
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