MCF52110CVM80J Freescale Semiconductor, MCF52110CVM80J Datasheet - Page 23
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MCF52110CVM80J
Manufacturer Part Number
MCF52110CVM80J
Description
IC MCU 128K FLASH 80MHZ 81MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xxr
Datasheet
1.MCF52110CAF80.pdf
(56 pages)
Specifications of MCF52110CVM80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
81-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52110CVM80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.12
Table 14
1.13
Table 15
1.14
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Freescale Semiconductor
General Purpose Timer
PWM Output Channels
Signal Name
Development Serial
Input/Output
Test Mode Select
Test Data Output
Test Data Input
describes the general purpose timer signals.
describes the PWM signals.
Signal Name
JTAG Enable
Signal Name
Breakpoint
Test Reset
Test Clock
General Purpose Timer Signals
Pulse Width Modulator Signals
Debug Support Signals
Clock
Abbreviation
Abbreviation
Abbreviation
GPT[3:0]
PWM[7:0]
JTAG_EN
DSCLK
TRST
TCLK
BKPT
TDO
TMS
TDI
MCF52110 ColdFire Microcontroller, Rev. 1
Table 16. Debug Support Signals
Pulse width modulated output for PWM channels.
Inputs to or outputs from the general purpose timer module.
Select between debug module and JTAG signals at reset.
This active-low signal is used to initialize the JTAG logic
asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
Table 15. PWM Signals
Table 14. GPT Signals
Function
Function
Function
Family Configurations
I/O
I/O
O
O
I
I
I
I
I
I
I
I/O
I/O
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