MCF52110CVM80J Freescale Semiconductor, MCF52110CVM80J Datasheet - Page 21
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MCF52110CVM80J
Manufacturer Part Number
MCF52110CVM80J
Description
IC MCU 128K FLASH 80MHZ 81MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xxr
Datasheet
1.MCF52110CAF80.pdf
(56 pages)
Specifications of MCF52110CVM80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
81-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52110CVM80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.6
Table 8
1.7
Table 9
1.8
Table 10
Freescale Semiconductor
Synchronous Peripheral
QSPI Synchronous
QSPI Synchronous
QSPI Serial Clock
External Interrupts
describes the external interrupt signals.
describes the QSPI signals.
Serial Data Input
describes the I
Signal Name
Serial Output
Signal Name
Chip Selects
Signal Name
Serial Clock
Serial Data
External Interrupt Signals
Queued Serial Peripheral Interface (QSPI)
I
2
1
2
C I/O Signals
The PLL pre-divider (CCHR+1) reset value is 1 and the PLL input reference range is 2–10 MHz,
so in order to boot with the PLL enabled, the external clock or crystal frequency needs to be less
than 10 MHz. MCF5211x devices cannot boot with PLL enabled from an external clock or
crystal oscillator with frequency greater than 10 MHz. This constraint does not apply to booting
with PLL disabled.
Cannot boot from the Internal 8 MHz Relaxation oscillator with the PLL enabled. Refer Note1.
Thus this mode has been removed from the table.
2
C serial interface module signals.
Table 9. Queued Serial Peripheral Interface (QSPI) Signals
QSPI_CS[3:0] QSPI peripheral chip select; can be programmed to be active high or
Abbreviation
Abbreviation
Abbreviation
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
QSPI_CLK
QSPI_DIN
IRQ[7:1]
SDAn
SCLn
MCF52110 ColdFire Microcontroller, Rev. 1
Table 8. External Interrupt Signals
External interrupt sources.
Open-drain clock signal for the for the I
In master mode, this clock is driven by the I
is in slave mode, this clock becomes the clock input.
Open-drain signal that serves as the data input/output for the I
interface.
driven on the rising or falling edge of QSPI_CLK.
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
low.
Table 10. I
2
C I/O Signals
Function
Function
Function
2
C interface. When the bus is
2
C module; when the bus
Family Configurations
2
C
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
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