MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 87
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1. Read: Anytime. The data source is depending on the data direction value.
2.3.40
Freescale Semiconductor
Function
Address 0x0258
Write: Anytime
Altern.
Field
Reset
PTP
PTP
PTP
4-0
7
5
W
R
Port P general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port P general purpose input/output data—Data Register, PWM input/output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port P general purpose input/output data—Data Register, PWM output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
• The PWM function takes precedence over the general purpose I/O function if the related channel or the
• Pin interrupts can be generated if enabled in input or output mode.
• The PWM function takes precedence over the general purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
PTP7
Port P Data Register (PTP)
emergency shut-down feature is enabled.
—
0
7
—
0
0
6
Table 2-35. PTP Register Field Descriptions
Figure 2-38. Port P Data Register (PTP)
S12P-Family Reference Manual, Rev. 1.13
PWM5
PTP5
5
0
PWM4
PTP4
0
4
Description
PWM3
PTP3
0
3
PWM2
PTP2
0
2
Port Integration Module (S12PPIMV1)
Access: User read/write
PWM1
PTP1
0
1
PWM0
PTP0
0
0
87
(1)
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