MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 473
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
This timer can be used for many purposes, including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from microseconds to many seconds.
This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The
input capture function is used to detect a selected transition edge and record the time. The output compare
function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator
Freescale Semiconductor
Revision
Number
V02.04
V02.05
V02.06
Introduction
Revision Date
26 Aug 2009
1 Jul 2008
9 Jul 2009
14.3.2.2/14-480
14.3.2.3/14-481
14.3.2.4/14-482
14.4.2/14-497
14.4.3/14-497
14.4.2/14-497
14.4.3/14-497
14.1.2/14-474
14.4.3/14-497
14.3.2.12/14-
14.3.2.13/14-
14.3.2.16/14-
14.3.2.12/14-
14.3.2.13/14-
14.3.2.15/14-
14.3.2.16/14-
14.3.2.19/14-
14.3.2.15/14-
Sections
Affected
488
489
492
488
489
491
492
494
491
S12P-Family Reference Manual, Rev. 1.13
Table 14-1. Revision History
- Revised flag clearing procedure, whereby TEN bit must be set when clearing
flags.
- Revised flag clearing procedure, whereby TEN or PAEN bit must be set
when clearing flags.
- Add fomula to describe prescaler
- Correct typo: TSCR ->TSCR1
- Correct reference: Figure 1-25 -> Figure 1-31
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
Description of Changes
473
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