MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 342
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Pulse-Width Modulator (PWM8B6CV1) Block Description
10.3.2.7
This register is reserved for factory testing of the PWM module and is not available in normal modes.
342
Module Base + 0x0006
CON45
CON23
CON01
PSWAI
Reset
PFRZ
Field
6
5
4
3
2
W
R
Concatenate Channels 4 and 5
0 Channels 4 and 5 are separate 8-bit PWMs.
1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order
Concatenate Channels 2 and 3
0 Channels 2 and 3 are separate 8-bit PWMs.
1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high-order
Concatenate Channels 0 and 1
0 Channels 0 and 1 are separate 8-bit PWMs.
1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high-order
PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the
input clock to the prescaler.
0 Allow the clock to the prescaler to continue while in wait mode.
1 Stop the input clock to the prescaler whenever the MCU is in wait mode.
PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the
prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode
the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function
to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that after normal
program flow is continued, the counters are re-enabled to simulate real-time operations. Because the registers
remain accessible in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode.
0 Allow PWM to continue while in freeze mode.
1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.
Reserved Register (PWMTST)
0
0
7
byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM
(bit 5 of port PWMP). Channel 5 clock select control bit determines the clock source, channel 5 polarity bit
determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit
determines the output mode.
byte and channel 3 becomes the low-order byte. Channel 3 output pin is used as the output for this 16-bit PWM
(bit 3 of port PWMP). Channel 3 clock select control bit determines the clock source, channel 3 polarity bit
determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit
determines the output mode.
byte and channel 1 becomes the low-order byte. Channel 1 output pin is used as the output for this 16-bit PWM
(bit 1 of port PWMP). Channel 1 clock select control bit determines the clock source, channel 1 polarity bit
determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit
determines the output mode.
= Unimplemented or Reserved
0
0
6
Figure 10-9. Reserved Register (PWMTST)
Table 10-9. PWMCTL Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
0
0
5
0
0
4
Description
0
0
3
0
0
2
Freescale Semiconductor
0
0
1
0
0
0
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