MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 487
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
14.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000C
Module Base + 0x000D
C7I:C0I
Reset
Reset
Field
7:0
W
W
R
R
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
C7I
TOI
0
0
7
7
= Unimplemented or Reserved
C6I
Figure 14-19. Timer System Control Register 2 (TSCR2)
0
0
0
6
6
Figure 14-18. Timer Interrupt Enable Register (TIE)
S12P-Family Reference Manual, Rev. 1.13
Table 14-12. TIE Field Descriptions
C5I
0
0
0
5
5
C4I
0
0
0
4
4
Description
TCRE
C3I
0
0
3
3
Timer Module (TIM16B8CV2) Block Description
PR2
C2I
0
0
2
2
PR1
C1I
0
0
1
1
PR0
C0I
0
0
0
0
487
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