MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 229
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.3.2.19
The CPMUHTTR register configures the trimming of the S12CPMU temperature sense.
Read: Anytime
Write: Anytime
Freescale Semiconductor
0x02F7
HTTR[3:0]
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
Reset
HTOE
Field
details.
3–0
7
W
R
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Register (CPMUHTTR)
High Temperature Trimming Bits — See
0
7
= Unimplemented or Reserved
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
6
Bit
S12P-Family Reference Manual, Rev. 1.13
Increases V
Increases V
Increases V
Increases V
0
0
5
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 1-27
0
0
4
Trimming Effect
Description
for trimming effects.
S12 Clock, Reset and Power Management Unit (S12CPMU)
HTTR3
F
3
HTTR2
F
2
HTTR1
F
1
HTTR0
F
0
229
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