MC9S08QD2MSCR Freescale Semiconductor, MC9S08QD2MSCR Datasheet - Page 68
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MC9S08QD2MSCR
Manufacturer Part Number
MC9S08QD2MSCR
Description
IC MCU 8BIT 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08QD2MSCR
Core Processor
HCS08
Core Size
8-Bit
Speed
16MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08QD
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
128 B
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QD4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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Chapter 6 Parallel Input/Output Control
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2
Associated with the parallel I/O ports is a set of registers located in the high-page register space that
operate independently of the parallel I/O registers. These registers are used to control pullups, slew rate
and drive strength for the pins.
6.3
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
68
Pin Control — Pullup, Slew Rate and Drive Strength
Pin Behavior in Stop Modes
Port Read
BUSCLK
Data
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Figure 6-1. Parallel I/O Block Diagram
PTxDDn
D
D
PTxDn
Q
Q
1
0
Synchronizer
Output Enable
Output Data
Freescale Semiconductor
Input Data
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