MC9S08QD2MSCR Freescale Semiconductor, MC9S08QD2MSCR Datasheet - Page 125
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MC9S08QD2MSCR
Manufacturer Part Number
MC9S08QD2MSCR
Description
IC MCU 8BIT 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08QD2MSCR
Core Processor
HCS08
Core Size
8-Bit
Speed
16MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
4
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
S08QD
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
128 B
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QD4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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9.2
There are no ICS signals that connect off chip.
9.3
9.3.1
Freescale Semiconductor
IREFSTEN
IRCLKEN
IREFS
CLKS
Field
RDIV
7:6
5:3
2
1
0
Reset:
External Signal Description
Register Definition
W
R
ICS Control Register 1 (ICSC1)
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
00
01
10
11
Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits.
Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128
Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.
1 Internal reference clock selected
0 External reference clock selected
Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as
ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock
remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before
0 Internal reference clock is disabled in stop
entering stop
Output of FLL is selected.
Internal reference clock is selected.
External reference clock is selected.
Reserved, defaults to 00.
7
0
CLKS
Table 9-1. ICS Control Register 1 Field Descriptions
0
6
Figure 9-3. ICS Control Register 1 (ICSC1)
MC9S08QD4 Series MCU Data Sheet, Rev. 6
0
5
RDIV
0
4
Description
0
3
IREFS
1
2
Internal Clock Source (S08ICSV1)
IRCLKEN
0
1
IREFSTEN
0
0
125
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