ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 176
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ST10F269Z2Q6
Manufacturer Part Number
ST10F269Z2Q6
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Specifications of ST10F269Z2Q6
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Controller Family/series
ST10
No. Of I/o's
111
Ram Memory Size
12KB
Cpu Speed
40MHz
No. Of Timers
5
Embedded Interface Type
CAN, SSC, USART
Rohs Compliant
Yes
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-4833
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
201
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
745
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
20 000
The formula for SSC Clock Cycle time is: t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
V
The formula for SSC Clock Cycle time is: t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer
176/184
t
t
318p
t
t
t
t
t
t
t
t
t
t
t
CC
317p
Symbol
317
318
Symbol
310
311
312
313
314
315
316
317
318
= 5V ±10%, V
1
SR Read data setup time before latch
SR Read data hold time after latch edge,
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
edge,
(SSCPEN = 0)
phase
(SSCPEN = 0)
phase error detection on (SSCPEN = 1)
phase error detection on (SSCPEN = 1)
phase error detection off (SSCPEN = 0)
phase error detection off (SSCPEN = 0)
phase
SS
error
= 0V, CPU clock = 32MHz, T
Parameter
Parameter
error
detection
detection
310
310
off
off
= 4 TCL * (<SSCBR> + 1)
= 4 TCL * (<SSCBR> + 1)
Maximum Baud rate=6.25MBd
Maximum Baud rate=10MBd
Minimum
Minimum
109.375
78.125
A
41.25
(<SSCBR> = 0001h)
(<SSCBR> = 0001h)
52.5
52.5
125
31
= -40 to +125°C, C
6
–
–
–
0
6
Maximum
Maximum
45.25
10
10
–
–
–
–
–
–
–
–
–
–
L
= 50pF (TQFP144 devices)
(<SSCBR>=0001h-FFFFh)
(<SSCBR>=0001h-FFFFh)
t
t
2TCL + 10
Minimum
Minimum
2TCL + 6
310
310
4TCL +
6TCL +
15.625
15.625
8 TCL
Variable Baud rate
Variable Baud rate
/2 - 10
/2 - 10
6
–
–
–
0
6
262144 TCL
2 TCL + 14
Maximum
Maximum
ST10F269
10
10
–
–
–
–
–
–
–
–
–
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns