ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 169
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ST10F269Z2Q6
Manufacturer Part Number
ST10F269Z2Q6
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Specifications of ST10F269Z2Q6
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Controller Family/series
ST10
No. Of I/o's
111
Ram Memory Size
12KB
Cpu Speed
40MHz
No. Of Timers
5
Embedded Interface Type
CAN, SSC, USART
Rohs Compliant
Yes
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-4833
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
201
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
745
Company:
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
20 000
ST10F269
V
Table 51 : CLKOUT and READY Characteristics (TQFP144 devices)
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
Note
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
DD
Symbol
= 5V
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2t
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
A
and t
10%, V
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
C
refer to the next following bus cycle, t
SS
Parameter
= 0V, T
A
= -40 to + 125°C, C
1)
1)
2)
Minimum
-3 + t
31.25
9.625
5.625
45.25
Maximum CPU Clock
F
14
14
refers to the current bus cycle.
–
–
4
4
0
A
L
= 32MHz
= 50pF, TQFP144 devices
Maximum
+ t C + t
+7 + t
0 + 2t
31.25
–
–
4
4
–
–
–
–
–
A
A
F
2
2TCL + 14
Minimum
TCL – 10
TCL – 6
-3 + t
2TCL
1/2TCL = 1 to 32MHz
Variable CPU Clock
14
14
–
–
4
4
0
A
TCL - 15.625 +
2t
Maximum
A
+7 + t
+ t C + t
2TCL
–
–
4
4
–
–
–
–
–
A
F
2
169/184
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns