ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 120
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ST10F269Z2Q6
Manufacturer Part Number
ST10F269Z2Q6
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Specifications of ST10F269Z2Q6
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Controller Family/series
ST10
No. Of I/o's
111
Ram Memory Size
12KB
Cpu Speed
40MHz
No. Of Timers
5
Embedded Interface Type
CAN, SSC, USART
Rohs Compliant
Yes
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-4833
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
201
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
745
Company:
Part Number:
ST10F269Z2Q6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST10F269Z2Q6
Manufacturer:
ST
Quantity:
20 000
18 - SYSTEM RESET
Figure 59 : Minimum External Reset Circuitry
Figure 60 : External Reset Hardware Circuitry
Table 38 : PORT0 Latched Configuration for the Different Resets
Table 39 : PORT0 Bits Latched into the Different Registers After Reset
Notes: 1. Not latched from PORT0.
120/184
PORT0 bit
BUSCON0
PORT0 bit
X: Pin is sampled
-: Pin is not sampled
Software Reset
Watchdog Reset
Short Hardware Reset
Long Hardware Reset
Power-On Reset
SYSCON
RP0H
Internal
Name
Nebr.
Logic
Sample event
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
2
V
R0
C0
DD
V
R0
C0
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL
DD
+
X
X
X
h7
1
1
1
+
To Clock Generator
h6
X
X
X
1
1
1
RPD
ST10F269
RPD
RSTOUT
ST10F269
X
X
X
h5
1
1
1
X
X
-
-
-
To Port 4 Logic
X
X
X
h4
X
X
-
-
-
1
1
1
RSTOUT
RSTIN
X
X
-
-
-
X
X
h3
RSTIN
-
1
1
ACT0
X
X
X
X
X
BUS
To Port 6 Logic
X
X
h2
V
1
1
DD
C1
4
X
X
X
X
X
BYTDIS
CSSEL
CTL0
+
ALE
X
h1
Open - drain
Inverter
1
X
X
X
X
X
4
b)
R2
3
WRC BUSTYP BUSTYP
X
X
X
h0
-
1
1
1
X
X
X
X
X
WRCFG
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
D2
a)
BTYP
X
I7
PORT0
X
X
X
X
X
1
Hardware
Hardware
3
External
External
a) Manual hardware reset1
b) For automatic power-up and
X
X
X
X
X
BTYP
interruptible power-down mode
X
X
I6
External
Reset Source
1
1
X
X
X
X
X
X
X
X
I5
R
D1
1
1
1
X
X
X
-
-
Internal
BSL
X
X
I4
X
X
X
1
1
-
-
+
V
R1
DD
C1
X
X
X
X
X
X
I3
-
-
R
1
1
1
X
X
X
-
-
X
X
X
I2
ST10F269
R
1
1
1
Internal Internal
X
X
X
-
-
ADP
X
X
I1
1
1
X
X
X
-
-
EMU
X
X
I0
1
1