ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 116
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ST10F269Z2Q6
Manufacturer Part Number
ST10F269Z2Q6
Description
MCU 16BIT 256K FLASH 144PQFP
Manufacturer
STMicroelectronics
Series
ST10r
Specifications of ST10F269Z2Q6
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Controller Family/series
ST10
No. Of I/o's
111
Ram Memory Size
12KB
Cpu Speed
40MHz
No. Of Timers
5
Embedded Interface Type
CAN, SSC, USART
Rohs Compliant
Yes
Processor Series
ST10F26x
Core
ST10
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SSC, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
2 x 16 bit
Operating Supply Voltage
0.3 V to 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit x 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-4833
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18 - SYSTEM RESET
Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL)
Note
18.1.3 - Exit of Long Hardware Reset
- If the RPD pin level is low when the RSTIN pin
is sampled high, the MCU completes an
asynchronous reset sequence.
- If the RPD pin level is high when the RSTIN pin
is sampled high, the MCU completes a
synchronous reset sequence.
The system configuration is latched from PORT0
after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3
CPU clocks if PLL is bypassed) and in case of
external fetch, ALE, RD and R/W pins are driven
to their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Refer to
Table 38 for PORT0 latched configuration.
18.2 - Short Hardware Reset
A short hardware reset is a warm reset. It may be
generated synchronously to the CPU clock
(synchronous reset).
116/184
CPU Clock
RSTIN
RPD
RSTOUT
ALE
RD
PORT0
Internal reset signal
1) RSTIN rising edge to internal latch of PORT0 is 3 CPU
clock cycles (6 TCL) if the PLL is bypassed and the
2) RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after
reset.
3) If during the reset condition (RSTIN low), V
ST10 reset circuitry disables the bidirectional reset function and RSTIN pin is no more pulled low.
low. The reset is processed as an
asynchronous reset.
4 TCL
min.
200 A Discharge
12 TCL
max.
Internally pulled low
1024 TCL
RPD
voltage drops below the threshold voltage (typically 2.5V for 5V operation), the
If V
Reset is not entered.
RPD
Reset Configuration
2)
> 2.5V Asynchronous
The short hardware is triggered when RSTIN
signal duration is shorter or equal to 1038
TCL, the RPD pin must be pulled high.
To properly activate the internal reset logic of the
MCU, the RSTIN pin must be held low, at least,
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and RSTOUT pin is
driven low. After RSTIN level is detected, a short
duration of 12 TCL (6 CPU clocks) maximum
elapses, during which pending internal hold states
are cancelled and the current internal access
cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is
activated if bit BDRSTEN of SYSCON register
was previously set by software. This bit is always
cleared on power-on or after any reset sequence.
The internal reset sequence starts for 1024 TCL
(512 periods of CPU clock).
After that duration the pull-down of RSTIN pin for
the bidirectional reset function is released and the
RSTIN pin level is sampled high while RPD level is
high.
The short hardware reset ends and the MCU
restarts.To be processed as a short hardware
reset, the external RSTIN signal must last a
3)
prescaler is on (f
cycles (8 TCL).
1
6 or 8 TCL
2
3
4
CPU
1)
5
= f
for system start-up configuration
Latching point of PORT0
5 TCL
XTAL
6
7
/ 2), else it is 4 CPU clock
8
9
ST10F269