ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 153

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F273M
24.8.10
Note:
Figure 47. ST10F273M PLL jitter
PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency f
crystal failure occurrence without risking to go into an undefined configuration: The system
is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration
of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized
high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not
sufficient to get the PLL locked starting from free-running mode).
Table 64.
T
T
T
Symbol
PSUP
LOCK
JIT
T
±5
±4
±3
±2
±1
JIT
PLL start-up time
PLL lock-in time
Single period jitter
(cycle to cycle = 2 TCL)
0
0
PLL characteristics (V
Parameter
200
(1)
16MHz
(1)
400
24MHz
Stable V
Stable V
starting from free-running mode
6 sigma time period variation
(peak to peak)
DD
N (CPU clock periods)
= 5V ± 10%, V
600
32MHz
DD
DD
free
Conditions
and reference clock
and reference clock,
). This feature allows to recover from a
40MHz
800
SS
= 0V, T
1000
A
Electrical characteristics
= -40°C to +125°C)
-500
Min
1200
–
–
Value
64MHz
+500
Max
300
250
1400
153/182
Unit
µs
ps