ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 151

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F273M
Note:
24.8.9
Table 63.
The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 40 MHz.
Example 1
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Example 2
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PLL jitter
The following terminology is hereafter defined:
●
●
(P0H.7-5)
1
1
1
1
0
0
0
0
P0.15-13
f
P0(15:13) = ‘110’ (multiplication by 3)
PLL Input Frequency = 1 MHz
VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz
f
f
P0(15:13) = ‘100’ (multiplication by 5)
PLL Input Frequency = 2 MHz
VCO frequency = 80 MHz
PLL Output Frequency = 40 MHz (VCO frequency divided by 2)
f
Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T
where T
time period of the PLL output clock.
Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of T
T
minimum time difference between N + 1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N = 1, this becomes the single period
jitter.
1
1
0
0
1
1
0
0
XTAL
CPU
XTAL
CPU
max
1
0
1
0
1
0
1
0
= NOT VALID
= 40 MHz (no effect of Output Prescaler)
is the maximum time difference between N + 1 clock rising edges and T
= 4 MHz
= 8 MHz
XTAL frequency
Internal PLL divider mechanism
max
5.3 to 10.6 MHz
6.4 to 8 MHz
1 to 40 MHz
4 to 12 MHz
4 to 8 MHz
4 to 5 MHz
Reserved
is maximum time period of the PLL output clock and T
4 MHz
prescaler
f
f
XTAL
XTAL
Input
–
–
/ 4
/ 2
Multiply
by
64
48
64
40
40
PLL bypassed
PLL bypassed
PLL
Divide by
4
2
2
prescaler
Electrical characteristics
Output
f
PLL
–
–
/ 2
max
min
max
is the minimum
and T
CPU frequency
f
CPU
and T
f
f
f
f
f
f
XTAL
f
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
= f
min
min
XTAL
min
, where
x 10
151/182
x 4
x 3
x 8
x 5
x 1
/ 2
is the
,
x F