W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 70

• Manufacturer Part Number: W77E058A40DL
• Description: IC MCU 8-BIT 32K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40DL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

15. TIMED ACCESS PROTECTION
The W77E058 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait
state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If
left unprotected, errant code may write to the Watchdog control bits resulting in incorrect operation and
loss of control. In order to prevent this, the W77E058 has a protection scheme which controls the write
access to critical bits. This protection scheme is done using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,
during which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below
Example 1: Valid access
Example 2: Valid access
Example 3: Valid access
Example 4: Invalid access
TA
MOV
MOV
MOV
MOV
MOV
MOV
MOV
NOP
SETB EWT
MOV
MOV
ORL
MOV
MOV
NOP
NOP
CLR
REG
TA, #0AAh
TA, #055h
TA, #0AAh
TA, #055h
WDCON, #00h 3 M/C
TA, #0AAh
TA, #055h
TA, #0Aah
TA, #055h
WDCON, #00000010B 3M/C
TA, #0AAh
TA, #055h
POR
0C7h
3 M/C
3 M/C
3 M/C
3 M/C
1 M/C
2 M/C
3 M/C
3 M/C
3 M/C
3 M/C
1 M/C
1 M/C
2 M/C
; define new register TA, located at 0C7h
- 70 -
Note: M/C = Machine Cycles
W77E058A