W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 56

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W77E058A40DL

Manufacturer Part Number
W77E058A40DL
Description
IC MCU 8-BIT 32K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W77r
Datasheets

Specifications of W77E058A40DL

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, Serial Port
Peripherals
POR, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP
Cpu Family
W77
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
UART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

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12.3 Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled
by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the
Timer 0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling the clock,
and in defining the operating mode. The clock source for Timer/Counter 2 may be selected for either
the external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 or 4 (C/T2 = 0). The clock
is then enabled when TR2 is a 1, and disabled when TR2 is a 0.
12.3.1 Capture Mode
The capture mode is enabled by setting the CP RL
mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from FFFFh to
0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a
negative transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the
RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will
also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W77E058 allows hardware to reset
timer 2 automatically after the value of TL2 and TH2 have been captured.
div. by 4
div. by 64
div. by 1024 osc/256
Mode
Clock Source
TR0 = TCON.4
TR1 = TCON.6
GATE = TMOD.3
INT0 = P3.2
T0 = P3.4
osc/1
osc/16
input
1/12
1/4
T0M = CKCON.3
0
1
1
C/T = TMOD.2
0
Figure 13. Timer/Counter 0 Mode 3
/
- 56 -
2 bit in the T2CON register to a 1. In the capture
0
0
TH0
TL0
7
7
TF1
TF0
W77E058A
Interrupt
Interrupt

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