W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 23

• Manufacturer Part Number: W77E058A40DL
• Description: IC MCU 8-BIT 32K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40DL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Power Management Register
CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one
SWB:
XTOFF: Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can
ALE0FF: This bit disables the expression of the ALE signal on the device pin during all on-board
DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will
STATUS Register
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
Switchback Enable. Setting this bit allows an enabled external interrupt or serial port activity
to force the CD1,CD0 to divide by 4 state (0,1). The device will switch modes at the start of
the jump to interrupt service routine while a external interrupt is enabled and actually
recongnized by microcontroller. While a serial port reception, the switchback occurs at the
start of the instruction following the falling edge of the start bit.
only be set to 1 while the microcontroller is operating from the RC oscillator. Clearing this bit
restarts the crystal oscillator, the XTUP (STATUS.4) bit will be set after crystal oscillator
warmed-up has completed.
enable the on-chip 1KB MOVX SRAM.
0 = ALE expression is enable; 1 = ALE expression is disable
program and data memory accesses. External memory accesses will automatically enable
ALE independent of ALEOFF.
machine cycle. There are three modes including divide by 4, 64 or 1024. Switching
between modes must first go back devide by 4 mode. For instance, to go from 64 to 1024
clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle, and then
from 4 to 1024 clocks/machine cycle.
Bit:
Mnemonic: PMR
Mnemonic: STATUS
Bit:
CD1
7
7
-
CD1,
CD0
0
0
1
1
6
HIP
6
CD0
0
1
0
1
SWB
5
LIP
5
Clocks/machine Cycle
- 23 -
Reserved
XTUP
4
-
1024
4
64
4
XTOFF
SPTA1
Publication Release Date: April 17, 2007
3
3
ALE-OFF
Address: C4h
Address: C5h
SPRA1
2
2
W77E058A
SPTA0
1
-
1
Revision A10
SPRA0
DME0
0
0