W77E058A40DL Nuvoton Technology Corporation of America, W77E058A40DL Datasheet - Page 14

• Manufacturer Part Number: W77E058A40DL
• Description: IC MCU 8-BIT 32K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40DL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 32
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Timer Control
TF1:
TR1:
TF0:
TR0:
IE1:
IT1:
IE0:
IT0:
Timer Mode Control
GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and
C T
/
: Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set,
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
the timer counts high-to-low edges of the Tx pin.
Mnemonic: TCON
Mnemonic: TMOD
Bit:
Bit:
GATE
TF1
7
7
C T
TR1
6
6
/
TIMER1
TF0
M1
- 14 -
5
5
TR0
M0
4
4
GATE
IE1
3
3
Address: 88h
Address: 89h
C T
IT1
2
2
/
TIMER0
W77E058A
IE0
M1
1
1
IT0
M0
0
0