Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 72

• Manufacturer Part Number: Z8F0813HJ005EG
• Description: IC Z8 ENCORE MCU FLASH 8K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813HJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4182; Z8F0813HJ005EG

BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025203-0405
IRQ0 Enable High and Low Bit Registers
Reserved
Reserved
R/W
R
0
7
0
7
Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt
Request 0 register. Priority is generated by setting bits in each register.
Reserved—Must be 0.
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—Must be 0.
IRQ0ENH[x] IRQ0ENL[x] Priority
where x indicates the register bits from 0–7.
T1ENH
T1ENL
Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)
R/W
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
R/W
6
0
6
0
0
0
1
1
Table 37. IRQ0 Enable and Priority Encoding
T0ENH
T0ENL
R/W
R/W
5
0
5
0
0
1
0
1
P R E L I M I N A R Y
U0RENH
U0RENL
R/W
R/W
0
4
0
Disabled
Level 1
Level 2
Level 3
4
FC1H
FC2H
U0TENH
U0TENL
R/W
R/W
3
0
3
0
Description
Disabled
Low
Nominal
High
Reserved Reserved
Reserved Reserved
Z8 Encore!
R/W
R
0
2
0
2
Product Specification
®
R/W
R
1
0
1
0
Z8F0823 Series
Interrupt Controller
ADCENH
ADCENL
R/W
R/W
0
0
0
0
55