Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 129

• Manufacturer Part Number: Z8F0813HJ005EG
• Description: IC Z8 ENCORE MCU FLASH 8K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813HJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4182; Z8F0813HJ005EG

PS025203-0405
Caution:
Continuous Conversion
6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
Follow these steps for setting up the ADC and initiating continuous conversion:
1. Enable the acceptable analog input by configuring the general-purpose I/O pins for
2. Write the
3. Write to the
4. When the first conversion in continuous operation is complete (after 5129 system
In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the
ADC and the latency of the ADC and its digital filter. Step changes at the input are not
detected at the next output from the ADC. The response of the ADC (in all modes) is
limited by the input signal bandwidth and the latency.
–
–
powered-down.
alternate function. This action disables the digital input and output driver.
–
The bit fields in the ADC Control register may be written simultaneously:
–
–
–
–
–
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
–
11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}.
CEN resets to 0 to indicate the conversion is complete.
Write the
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in the
Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device)
Set CONT to 1 to select continuous conversion.
If the internal VREF must be output to a pin, set the REFEXT bit to 1. The
internal voltage reference must be enabled in this case.
Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in
Set CEN to 1 to start the conversions.
CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation.
ADC Control/Status Register 1
ADC Control Register 0
REFSELH
ADC Control Register 0
ADC Control/Status Register 1
P R E L I M I N A R Y
bit of the pair {
to configure the ADC for continuous conversion.
REFSELH
.
to configure the ADC
,
REFSELL
.
Z8 Encore!
} to select the internal
Product Specification
Analog-to-Digital Converter
®
Z8F0823 Series
112